This application is based on Japanese Patent Application Nos. 2000-253369 filed Aug. 24, 2000 and 2000-380782 filed Dec. 14, 2000, the contents of which are incorporated hereinto by reference.
1. Field of the Invention
The present invention relates to a process for manufacturing a self-aligned transistor for being applicable to fields of MIS (Metal Insulator Semiconductor) FETs (Field Effect Transistors) or the like.
2. Description of the Related Art
1. Conventional Example
A conventional process for manufacturing a self-aligned transistor will be described below.
First, a gate insulating film and a gate electrode are sequentially formed on a semiconductor substrate. Then, ion implantations of impurities are performed into the semiconductor substrate by using those layers as a mask. Subsequently, the impurities injected semiconductor substrate is activated by thermal annealing to form a gate area, a source area, and a drain area in a self-aligning manner, thereby producing a self-aligned transistor.
2. Problems of the Conventional Example
In producing the self-aligned transistor, materials of the gate insulating film and the gate electrode must not be destroyed or modified during a subsequent process of thermal treatment based on thermal annealing.
Thus, in the conventional manufacturing process, the gate insulating film is comprised of a silicon oxide film (SiO2), and the gate electrodes is comprised of polycrystalline silicon.
However, in recent years, efforts have been made to increase the speed of transistors in order to improve transistor performance thereof, by increasing a current driving capability, reducing a parasitic resistance, and restraining variations in a threshold voltage, etc.
A possible means for improving these electrical characteristics is to use a thermally intolerant material for the gate insulating film and the gate electrode. Moreover, in this case, for manufacturing costs, a conventional semiconductor manufacturing process technique is advantageously used as changelessly as possible.
In the above described conventional manufacturing process, however, such a thermally intolerant material cannot actually be used because the thermal treatment process is carried out after the gate insulating film has been formed.
An object of the present invention is to provide a process for manufacturing a self-aligned transistor, even if a thermally intolerant material is used as a material of a gate insulating film and the gate electrode, thereby producing high performance, high reliable and inexpensive transistor devices.
There is provided a process for manufacturing a self-aligned transistor comprising steps of:
forming a diffusion source layer including a diffusion source for diffusion on areas corresponding to a gate area, a source area, and a drain area;
forming a pattern, corresponding to the gate area, on the diffusion source layer, and further removing the diffusion source layer correspondence to the pattern to form the gate area;
diffusing the diffusion source included the diffusion source layer into both the source area and the drain area except the gate area, by using heat treatment;
forming a gate insulating film over both the gate area and the thermally diffused diffusion source layer, and further forming a gate electrode, comprised of metal, over the gate insulating film;
removing the diffusion source layer as well as the gate insulating film and the gate electrode formed on the diffusion source layer to form a gate stacking structure having both the gate insulating film and the gate electrode formed only according to the gate area.
The above and other objects, effects, features, and advantages of the present invention will become more apparent from the following description of embodiments thereof taken in conjunction with the accompanying drawings.